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  featur es ev ev ev ev ev ev ev ev ev ev ev ev ev 1-bit/4-bit modes of sd, mmc and sdio supported 8-bit generic cpu interface both dma and interrupt mode is supported for data transfer command buf fers to store command index and ar gument any byte size transfers supported. sector size can be set from 1 byte to 2048 bytes crc generation / checking supported for both command and data transactions compliant with sdio specification version 1.1 compliant with sd specification version 1.1 compliant with mmc specification version 2.0 using the sd/sdio/mmc communication protocol, one sdio or sd or mmc card is supported card detection / removal support w rite protect using mechanical switch interrupts for errors contact us india: i w ave systems t echnologies pvt. ltd., 7/b, 29th main, btm layout 2nd stage, bangalore 560 076. india ph : +91-80-26683700, 26786245, fax : +91-80-26685200 email : , w eb : japan: i w ave systems t echnologies, 8f kannai sumiyoshi building 3-29, sumiyoshi-cho, naka-ku, y okohama kanagawa, japan. ph : +81-45-227-7626, fax : +81-45-227-7646, email : , w eb : mktg@iwavesystems.com www .iwavesystems.com jp-mktg@iwavesystems.com www .iwavesystems.com/japan deliverables t echnical specification r tl v erilog synthesizable code comprehensive t est environment t echnical support and maintenance ev ev ev ev cor e application used as host controller for sd, mmc and sdio cards ev cor e benefits eases soc integration configurable for ease of use ev ev cpu sd/mmc/ sdio card command p a th da t a p a th cpu interface command tx - rx command path fsm command shifter crc gen / checker data path fsm data tx - rx data shifter crc gen / checker data fifo clock logic response fifo command p a th da t a p a th cpu interface command tx - rx command path fsm command shifter crc gen / checker data path fsm data tx - rx data shifter crc gen / checker data fifo clock logic response fifo i w -sd controller is an interface between any 8-bit processor and the sd/ mmc/ sdio card. the interface towards the sd card is realized by the sd protocol implemented in the controller . the main blocks in the controller are cpu interface, command path state machine, command transmitter/ receiver , data path state machine, data transmit/receive and clock logic. n o t e : t h e a b o v e v a l u e s a r e f o r 3 2 - b i t g e n e r i c c p u i n t e r f a c e . overview resour ce utilization summary b u s i n t e r f a c e a c t e l f a m i l y d e v i c e t i l e s c o r e u t i l i z a t i o n i /o c e l l s r a m u t i l i z a t i o n f r e qu e n c y p o w e r p r o a si c 3 a 3 p 6 0 0 3 4 4 9 2 4 . 9 5 % 5 7 3 7 . 5 0 % 2 0 m h z 7 5 . 1 1 2 m w i g l o o a g l 6 0 0 3 5 7 0 2 5 . 8 2 % 5 7 3 7 . 5 0 % 2 0 m h z 7 3 . 1 4 9 m w s d 1 . 1 / s d i o 1 . 1 / m m c 2 . 0 d c n l l e i w - s o t r o r block diagram i w -sd contr oller


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